1. Field of the Invention
The present invention generally relates to semiconductor fabrication processes. More particularly, the present invention relates to the field of fabricating floating gates for semiconductor devices.
2. Related Art
Semiconductor fabrication processes have made possible the fabrication of advanced integrated circuits on a semiconductor wafer. These semiconductor fabrication processes are complex, requiring extensive control and care to avoid fabricating defective integrated circuits. As the size of the advanced integrated circuits is reduced, new fabrication issues arise when utilizing semiconductor fabrication processes designed for fabricating larger scaled advanced integrated circuits.
In particular, the reduction in size of semiconductor devices such as flash memory devices has resulted in fabrication problems. Typically, the flash memory device includes a stacked gate structure, a source, and a drain. The stacked gate includes a tunnel oxide layer, a floating gate layer for storing charge, an ONO (Oxide-Nitride-Oxide) layer, and a control gate layer for programming and erasing the flash memory device.
FIG. 1A illustrates a conventional fabrication process for forming the floating gate of the flash memory device 100. As depicted in FIG. 1A, the floating gate 9 is formed by depositing a doped polycrystalline silicon layer 9 on the tunnel oxide layer Tox which is formed on the surface of the semiconductor substrate 2. The doped polycrystalline silicon layer 9 includes a dopant material such as an N-type dopant material. Additional semiconductor processes are performed to form the stacked gate structure, the source, and the drain of the flash memory device 100. Moreover, a plurality of thermal processes are performed on the flash memory device 100. These thermal processes include an oxidation process and an anneal process.
The flash memory device 100 of FIG. 1A is shown after the plurality of thermal processes have been performed in FIG. 1B. As depicted in FIG. 1B, the floating gate 9 has a grain structure comprising a short number of grains 6A-6C comprised of doped polycrystalline silicon. Here, there are three grains 6A, 6B, and 6C. Each grain 6A-6C has a different orientation with respect to the tunnel oxide layer Tox. The grains 6A-6C are separated by grain boundaries 5. Moreover, each grain 6A-6C is large with respect to the size of the floating gate 9.
At the floating gate/tunnel oxide interface, the plurality of thermal processes causes the tunnel oxide layer Tox to grow via an oxidation process. The oxidation rate with respect to each grain 6A-6C is different. As shown in FIG. 1B, the oxidation rate at the grain 6A/tunnel oxide Tox interface is larger than the oxidation rates at the grain 6B/tunnel oxide Tox interface or the grain 6C/tunnel oxide Tox interface. Hence, at the grain 6A/tunnel oxide Tox interface, the thickness of the tunnel oxide Tox is significantly larger than at the grain 6B/tunnel oxide Tox interface or at the grain 6C/tunnel oxide Tox interface. The dashed area 3 demonstrates that there is a significant encroachment of the tunnel oxide Tox into the grain 6A of the floating gate 9.
As a result, the tunnel oxide Tox does not have a uniform thickness. This degrades the performance of the flash memory device 100 and impairs control of the flash memory device 100.